ds-104 rev d 3.7 saronix nth / nch series saronix crystal clock oscillator technical data hcmos 141 jefferson drive ? menlo park, ca 94303 ? usa ? 650-470-7700 ? 800-227-8974 ? fax 650-462-9894 500 khz to 100 mhz frequency stability: frequency range: 20*, 25, 50 or 100 ppm over all conditions: calibration tolerance, operating temperature, input voltage change, load change, aging, shock and vibration. actual size description a crystal controlled, low current oscil- lator providing precise rise and fall times to drive high speed hcmos and nmos microprocessors. the tri- state function on the nth enables the output to go high impedance. can drive both high speed cmos and ttl. device is packaged in a 14 or an 8-pin dip compatible resistance welded, all metal grounded case, to reduce emi. applications & features clock 16 and 32 bit microprocessors tri-state output on nth hcmos compatible grounded, all metal full size or half size case this versatile hcmos product is also available as a 3v surface mount plastic version, a metal double sealed version, and a gull wing (to 80 mhz) version ? ? ? ? ? mechanical: shock: solderability: terminal strength: vibration: solvent resistance: resistance to?soldering heat: mil-std-883, method 2002, condition b mil-std-883, method 2003 mil-std-202, method 211, conditions a & c mil-std-883, method 2007, condition a mil-std-202, method 215 mil-std-202, method 210, condition a, b or c ( i or j for gull wing) output waveform 80% v dd 1 level 0 level 50% v dd 20% v dd 2.5 vdc 1.5 vdc 0.5 vdc gnd v dd t r t f t f t r symmetry symmetry cmos ttl environmental: gross leak test: fine leak test: thermal shock: moisture resistance: mil-std-883, method 1014, condition c mil-std-883, method 1014, condition a2 <5 x 10 -8 atm cc/sec mil-std-883, method 1011, condition a mil-std-883, method 1004 tri-state logic table (nth only) pin 1 input logic 1 or nc logic 0 or gnd pin 8 (5) output oscillation high impedance required input levels on pin 1: logic 1 = 3.0 v min logic 0 = 0.5v max output drive: hcmos symmetry: rise and fall times: logic 0: logic 1: load: jitter: ttl see part numbering guide 6ns max to 25 mhz, 0.5 to 2.5v 5ns max 25+ to 100 mhz 0.5 v max v cc -0.6v min 10 ttl to 50 mhz, 5 ttl 50+ to 100 mhz 8ps max rms period jitter, 1ps max 1 s cycle-to-cycle jitter see part numbering guide 8ns max to 25 mhz, 20% to 80% v dd 5ns max 25+ to 100 mhz 10% v dd max 90% v dd min 50 pf to 50 mhz, 30 pf 50+ to 70 mhz, 15 pf 70+ to 100 mhz 8ps max rms period jitter, 1ps max 1 s cycle-to-cycle jitter symmetry: rise and fall times: logic 0: logic 1: load: jitter: temperature range: operating: storage: supply voltage: recommended operating: +5vdc 10% -55 to +125c 0 to +70c or -40 to +85c supply current: 0.5 to 8 mhz: 8+ to 25 mhz: 25+ to 50 mhz: 50+ to 100 mhz: 12ma 20ma 35ma 50ma * see part numbering guide
ds-104 rev d 3.8 saronix nth / nch series saronix crystal clock oscillator technical data hcmos 141 jefferson drive ? menlo park, ca 94025 ? usa ? 650-470-7700 ? 800-227-8974 ? fax 650-462-9894 all specifications are subject to change without notice. package details part numbering guide 20.6 .810 max 5.08 .200 max .46.08 .018.003 15.24.13 .600.005 12.19.13 .480.005 4.57.13 .180.005 13.0 .510 (4) glass insulators pin 7 gnd pin 8 output half size package max 0.9 .036 full size package pin 1 tri-state - nth n/c - nch max pin 14 +5vdc 7.62.13 .300.005 120 120 120 pin 1 tri-state - nth n/c - nch 1.5 .059 13.0 .510 max pin 4 gnd 1.5 .059 pin 8 +5vdc 6.0 .236 pin 5 output 7.62.20 .300.008 7.62.20 .300.008 5.08 .200 max .46.051 .018.002 0.9 .036 max 10.87 .428 max 13.0 .510 max saronix saronix marking format ** includes date code, frequency & model denotes pin 1 6.35.51 .250.020 6.35.51 .250.020 scale: none (dimensions in ) mm inches denotes pin 1 ** exact locations of items may vary marking format ** includes date code, frequency & model test circuits ma m power supply v m oscillator pin 14 (8) test point pin 8 (5) v cc out gnd pin 7 (4) pin 1 (1) * tri-state input (nth only) note a: c l includes probe and fixture capacitance *( ) indicates pin numbers for half-size package hcmos (used at saronix) c l = 50pf to 50 mhz 30 pf above 50 mhz (note a) pin 14 (8) v m test point v cc out oscillator pin 8 (5) gnd pin 7 (4) pin 1 (1) * power supply ma m c l = 15 pf (note a) r l = 390 w mmbd7000 or equiv tri-state input (nth only) note a: c l includes probe and fixture capacitance *( ) indicates pin numbers for half-size package ttl (optional load) t = tri-state c = pin 1 n/c frequency series h = cmos compatible n h 9 ? xx.xxxx symmetry / temperature range 0 = 40/60%, 0 to +70c 2 = 40/60%, -40 to +85c 4 = 45/55%, -40 to +85c, ttl 0.5 to 40 mhz only 6 = 45/55%, 0 to +70c, ttl 0.5 to 50 mhz only a = 45/55%, 0 to +70c, cmos 0.5 to 70 mhz only c = 45/55%, -40 to +85c, cmos 0.5 to 50 mhz only frequency range 3 = 0.5 to 6 mhz 6 = 6+ to 24 mhz 8 = 24+ to 100 mhz stability tolerance aa = (10+10) ppm * (0 to 70c only) a = 25 ppm (0 to 70c only) b = 50 ppm c = 100 ppm package 0 = full size, thru hole 9 = half size, thru hole ** j = half size, gull wing ** n = half size, gull wing, spanked leads * 10 ppm over operating temperature range plus 10 ppm over all other conditions ** 80 mhz max example pn: nth080c - 32.0000
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